1. Field of Invention
The present invention relates generally to operation of switching half-bridges, and relates more particularly to half-bridge gate drivers with high voltage offset detection.
2. Description of Related Art
High voltage half-bridge driver circuits are used in various applications such as motor drives, electronic ballasts for fluorescent lamps and power supplies. The half-bridge circuits employ a pair of totem pole connected transistors that are placed across a high voltage DC power supply. The schematic in FIG. 1 shows a simple half-bridge circuit. Transistors M1 and M2 are power devices with a midpoint connection, node “A”, that provides the output that is connected to the load. Each of transistors, M1, M2, has a gate drive buffer (DRV1 and DRV2, respectively) that supplies a gate signal to turn transistors M1, M2 on or off.
In various applications, it is desirable to observe the midpoint of the half-bridge output, node A, to determine when node A has transitioned from a high state to a low state or from a low state to a high state. An exemplary application is an electronic ballast for a fluorescent lamp. A simplified schematic of an electronic ballast 20 is shown in FIG. 2. Ballast 20 supplies power to a load connected to the half-bridge at node A, which load consists of a resonant circuit including an inductor L1, a capacitor C1 and a fluorescent lamp LAMP1. During operation, ballast 20 drives transistors M1, M2 to alternately switch on and off to cause current to build in the resonant load circuit connected to node A. For example, when transistor M1 turns on, the voltage at node A is pulled to the potential of the upper DC bus voltage and current begins to build in the resonant load. When transistor M1 is switched off, the current flowing in the resonant load causes the voltage at node A to slew towards a lower potential. It is assumed that the half-bridge switches at a frequency that is greater than the resonant frequency of the load circuit. After some “dead-time” delay transistor M2 is turned on and the voltage at node A is pulled to the lower DC bus voltage which is typically zero volts. The dead-time delay prevents transistors M1, M2 from both being on at the same time, which would cause a short circuit.
The slewing of the voltage at node A, prior to the turn on of transistor M2, will take some finite amount of time to completely transition from the upper DC bus voltage to the lower DC bus voltage. Under certain conditions, the voltage at node A may not have completely transitioned to the lower potential at the time transistor M2 is turned on. In this case, transistor M2 will pull the voltage at node A to the lower DC bus voltage. This so-called “hard-switching” is a source of switching losses and will cause heating of the half-bridge transistors M1 and M2, which may eventually lead to failure of transistors M1 and M2.
The switching losses can be minimized by ensuring that the voltage at node A has completely transitioned to the lower DC bus voltage prior to the turn on of transistor M2. One way to eliminate hard-switching by ensuring complete transition of the voltage at node A is to increase the dead-time delay between the turn off of transistor M1 (M2) and the turn on of transistor M2 (M1).
Another possibility for eliminating the hard-switching is to decrease the effective capacitive loading at node A. However, these two above-mentioned alternatives represent significant drawbacks in that the speed of switching is potentially reduced, or the lamp rating is potentially reduced.